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RISC-V Page 6

RISC-V Page 6
Free development tools for Gigadevice RISC-V microcontrollers
Free development tools for Gigadevice RISC-V microcontrollers
Business news |
GigaDevice in China has signed a deal with Segger for developers to use the Embedded Studio development tool free of…
Renesas unveils first generation 32-bit RISC-V CPU core
Renesas unveils first generation 32-bit RISC-V CPU core
New Products |
The Renesas RISC-V CPU achieves an impressive 3.27 CoreMark/MHz performance, outperforming similar architectures on the market. …
Renesas samples its first general purpose 32bit RISC-V chip
Renesas samples its first general purpose 32bit RISC-V chip
Technology News |
Renesas Electronics is sampling its first general purpose 32bit microcontroller based on its own RISC-V instruction set architecture (ISA) core. …
Imagination GPU for Ventana 4nm RISC-V chiplets
Imagination GPU for Ventana 4nm RISC-V chiplets
Business news |
Ventana Micro Systems is using GPU cores from Imagination Technologies in the UK for data centre and automotive RISC-V chip designs. The…

The EPAC1.5 – a significant milestone in high-performance computing
The EPAC1.5 – a significant milestone in high-performance computing
Market news |
The successful bring-up of EPAC 1.5 is a major step in the development of the EPI common platform EPAC1.5 is a collection of RISC-V based accelerators designed to push the…
Infineon backs Synopsys RISC-V processor IP launch
Infineon backs Synopsys RISC-V processor IP launch
Technology News |
Synopsys has launched three families of 32bit and 64bit processor cores using the RISC-V open instruction set architecture alongside its ARC cores. The Synopsys ARC-V cores range from the 32bit…
High performance GPU cores for cloud gaming with RISC-V
High performance GPU cores for cloud gaming with RISC-V
Technology News |
Imagination Technologies in the UK has launched a line of high-performance GPU IP with support for DirectX for cloud-based streaming gaming systems The IMG DXD includes a hardware-based implementation of DirectX…
Trio team up to drive RISC-V ASIL-compliant automotive silicon
Trio team up to drive RISC-V ASIL-compliant automotive silicon
News |
TASKING, Andes, and MachineWare to support RISC-V SoC design teams in the realm of firmware and MCAL development.
Semidynamics and Arteris to accelerate AI RISC-V SoC development
Semidynamics and Arteris to accelerate AI RISC-V SoC development
Technology News |
Arteris and Semidynamics partnership enhances the flexibility and highly configurable interoperability of RISC-V processor IP with system IP.
Tasking teams for Andes automotive RISC-V verification
Tasking teams for Andes automotive RISC-V verification
Business news |
Tasking in Germany has teamed up with Machineware to provide verification models and tools for the Andes RISC-V processor cores. Tasking’s system-level verification and debugging tools now support the Andes…
Semidynamics to use Arteris interconnect IP for RISC-V chips
Semidynamics to use Arteris interconnect IP for RISC-V chips
Business news |
Semidynamics is working with interconnect IP supplier Arteris on next generation RISC-V system on chip designs. The two are aiming to have a demonstrator platform in early 2024 using the…
Imperas updates RISC-V models, verification and tools
Imperas updates RISC-V models, verification and tools
Technology News |
The RISC-V processor models, ImperasDV processor verification and virtual platform products enable architecture exploration, implementation and software development.
Codasip delivers first commercial CHERI processor using RISC-V
Codasip delivers first commercial CHERI processor using RISC-V
Technology News |
German RISC-V processor designer Codasip has launched the first commercial implementation of CHERI with fine-grained memory protection for advanced security. The Capability Hardware Enhanced RISC Instructions (CHERI) technology was developed…
Google readies Android for RISC-V
Google readies Android for RISC-V
Business news |
Google is preparing developers for a version of Android that runs on processors using the RISC-V instruction set. Google started accepting patches for RISC-V last November, and has now begun…
Imperas to provide model of Tenstorrent Ascalon RISC-V core
Imperas to provide model of Tenstorrent Ascalon RISC-V core
Business news |
Imperas Software has developed a model of the Tenstorrent Ascalon processor core based around the RISC-V instruction set. As with other areas of abstraction during the complex SoC design process,…
SiFive lays off 20% of staff, re-aligns business
SiFive lays off 20% of staff, re-aligns business
Business news |
RISC-V processor architecture pioneer SiFive Inc. (Santa Clara, Calif.) has laid off about 20 percent of its staff and is “re-aligning” its business. Reportedly the 20 percent…
Fully-coherent RISC-V Tensor unit boosts AI applications
Fully-coherent RISC-V Tensor unit boosts AI applications
Technology News |
Based on fully optimised 64-bit fully customisable RISC-V cores, the RISC-V Tensor unit increases AI performance 128 times compared to using a scalar core.
First fully coherent RISC-V Tensor unit for AI chip design
First fully coherent RISC-V Tensor unit for AI chip design
Technology News |
SemiDynamics in Spain has developed a RISC-V Tensor Unit for AI chip design based on its fully customisable 64bit cores. The RISC-V Tensor unit is integrated into the cache sub-system,…
Qualcomm, Google confirm RISC-V wearable chip
Qualcomm, Google confirm RISC-V wearable chip
Business news |
After persistent rumours, Qualcomm Technologies has confirmed it is working with Google on a RISC-V chip for wearables for use with Wear OS. The development will help pave the way…
RISC-V processor family targets custom compute
RISC-V processor family targets custom compute
New Products |
Highly configurable, high-performamnce family of RISC-V baseline processors includes application and embedded cores.
Latest SiFive RISC-V cores to boost AI workloads
Latest SiFive RISC-V cores to boost AI workloads
Market news |
SiFive launched a pair of RISC-V CPU cores aimed at high-performance and AI/ML applications SiFive, Inc., the pioneer and leader of RISC-V computing announced two new products designed to address…
Partnership creates RISC-V multi-core environment
Partnership creates RISC-V multi-core environment
Business news |
An advanced multi-core fully-tested RISC-V environment and CHI interconnect enables chips to be easily created for applications such as AI and ML.
SemiDynamics teams for multicore RISC-V chiplet boost
SemiDynamics teams for multicore RISC-V chiplet boost
Business news |
Semidynamics in Spain has teamed up with SignatureIP in the US to combine multi-core RISC-V IP with CHI interconnect for the development of the latest chiplet AI chips. SignatureIP’s Coherent…
Codasip picks Verilock for secure hardware authentication
Codasip picks Verilock for secure hardware authentication
Business news |
Hardware authentication implements future-proof security functionality based on patented Entropy Extraction Device (EED) technology.
Intel launches compact RISC-V Nios processor core
Intel launches compact RISC-V Nios processor core
New Products |
Intel has launched a new, compact soft core for its FPGA devices based on the RISC-V open instruction set architecture. The Nios V/c compact microcontroller is the smallest core in…
NXP says R&D expansion still depends on level of public funding
NXP says R&D expansion still depends on level of public funding
News |
NXP Semiconductors NV (Eindhoven, The Netherlands) has said it is planning to increase its European R&D but the final investment decision is still dependent on how much money national ministries…
Andes ships RISC-V vector IP for data centre transformer AI chips
Andes ships RISC-V vector IP for data centre transformer AI chips
Technology News |
Andes Technology in Taiwan is shipping a high performance 64bit multicore RISC-V vector design that it developed for large language model datacentre AI chips. The AX45MPV is the third generation…
MIPS to Drive RISC-V Market Penetration and Innovation
MIPS to Drive RISC-V Market Penetration and Innovation
Market news |
MIPS, a leading developer of high- performance RISC-V compute IP, has announced embedded systems industry veteran Sameer Wasson as the company’s new CEO Before joining MIPS, Wasson spent 18…


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