Nvidia taps Cadence power analysis tool as it respins Rubin chip
Cette publication existe aussi en Français
Cadence Design Systems has developed a Dynamic Power Analysis (DPA) app that can scale to chip designs with over 40 billion gates such as the latest Rubin GPU from Nvidia.
The DPA runs on the Palladium Z3 emulator to assess the dynamic power consumption of a design across billions of cycles in a few hours with 97 percent accuracy.
Power analysis is one of the major challenges for AI chips such as Nvidia’s Blackwell and Rubin GPUs. The varying AI workloads stress different part of the chip design at different times, making full chip analysis vital across as many cycles as possible, before the chip commits to silicon.
Early modelling of the power consumption of a chip allows engineers to improve the energy efficiency while avoiding delays from over- or under-sizing the power network.
This has been highlighted this week as Nvidia’s next generation Rubin chip has been reported to be need a respin. The chip had taped out with TSMC on the N3P high performance 3nm process in June. Reports now say an additional tapeout has been required to boost the performance to match a competing processor planned by AMD, which would indicate a respin of the underlying silicon design rather than the metal layers.
“We think it is very likely that Rubin will be delayed,” said Sherman Shang, an analyst at Fubon Financial, in a research note. “The first version of Rubin was already taped out in late June, but Nvidia is now redesigning the chip to better match AMD’s upcoming MI450.”
A proposed tapeout in late September would push the first samples into 2026, but this would still keep Nvidia on track for shipments towards the end of next year as originally planned. The company said it was on track with its development.
“We think the next tape out schedule will be in late September or October, and based on the tape out schedule, the Rubin volume will be limited in 2026,” said Shang.
The DPA power app works with the Cadence Palladium Z3 Enterprise Emulation Platform which is based on an array of custom emulation processors. This array emulates the RTL and gate-level design of a chip of up to 48bn gates. This provides chip-level power estimation to identify peaks and calculate averages on long processing runs to allow designers to balance the power consumption with the performance.
This is especially important as the Rubin GPU die is expected to reach a power consumption of around 700W on the N3P process which is not optimised for power. The multi-chip Rubin with HBM4 memory is expected to reach 1.8kW while the quad-chip Rubin Ultra is expected to reach 3.6kW. This highlights the challenge of providing more performance in the same thermal envelope, which is why the collaboration on the power analysis was key.
The power analysis is also key to the packaging of the devices on a substrate using the TSMC System on Integrated Circuit (SoIC) process, rather than the CoWoS chip on wafer on substrate process used by the current Blackwell GPU.
Cadence first implemented a DPA app on the Z1 back in 2016, long before the need for analysis of AI chips. The DPA supports the Common Power Format (CPF) and IEEE 1801 power formats
The emulator, introduced at the end of 2024, uses the Nvidia BlueField data processing unit (DPU) and Quantum Infiniband interconnect system to link to the Protium X3 FPGA prototyping system which is based on the AMD Ultrascale FPGAs. The FPGAs run the synthesised RTL of the design to allow software to run on the design before the silicon is available.
“Nvidia has utilised Cadence Palladium Emulation for many years for our early software development, hardware-software verification and debug tasks,” said Narendra Konda, vice president, hardware engineering at Nvidia.
“Cadence and NVIDIA are building on our long history of introducing transformative technologies developed through deep collaboration,” said Dhiraj Goswami, corporate vice president and general manager at Cadence. “This project redefined boundaries, processing billions of cycles in as few as two to three hours. This empowers customers to confidently meet aggressive performance and power targets and accelerate their time to silicon.”
Cadence Palladium web page; www.nvidia.com
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
