Europe’s stealth leading-edge process technology
Europe has been at the forefront of semiconductor process technology for 40 years, but recently the calls to have leading edge technology in the region have grown louder.
For the last 20 years, a technology has been developed in the region that provides leading edge performance and can be manufactured in Europe. That technology is fully depleted silicon-on-insulator (FD-SOI), and the latest pilot line at CEA-Leti in Grenoble, France, promises to deliver the same performance as today’s 3nm technology, with lower cost and lower power consumption.
This process can be manufactured in Europe which is a critical step forward, not just for the automotive and industrial markets, but for chips for the exploding AI market where the region lags behind.
However the fact that FD-SOI can be a leading edge process for AI chips is perhaps not well known, as it has been focussed on analog mixed signal and radio devices.
At the same time, imec in Belgium has worked with leading chip makers over the years to develop leading edge technology, down to the coming 2nm technology and beyond (see below). But the chips are not made here, but in Taiwan and Korea.
Jean-Rene Lequepeys, CTO of CEA-Leti Image: CEA-Leti
“It’s the best technology for mixed signal and the best for power consumption, cost and environmental impact,” Jean-René Lequepeys, Chief Technology Officer (CTO) and deputy director of CEA-Leti tells eeNews Europe.
But it can also be used for digital logic, including AI accelerators, as an alternative to the power-hungry graphics processor units (GPUs) that currently dominate AI.
“We need to use the right technology for the right function, its what we have to do if you want to optimise performance and optimise cost,” he said. “Shrinking the transistors is not the only way to get more computing power, we need to look at alternative ways. GPU technology was used for AI as it was available as it was used for gaming, but we now know that it is not the way forward for AI. We need a new way to mix technologies, mixing non-volatile memories, and stacking technologies.”
He points to the failure of Dennard scaling that has previously driven the power density in complex chips.
“Today when we shrink technologies it costs a lot and we only gain 10 or 15% in the performance so we know that scaling is not the answer. The five technologies in the pilot line could be combined to deliver disruptive architectures with much more performance,” he said.
“We have two ways of bringing new power computing. If we look at 3D the vertical dimension can be used for more density. If we put on another layer of FD-SOI on top of 7nm FD-SOI we have the performance of a 5nm or 3nm node and if we stack three or four chips with three or four levels we increase the performance and the computing power and reduce the power consumption – my feeling is this is the way to go rather than developing a 2nm chip with an NRE of $700m and a huge team of maybe 200 engineers.”
Memory is a key element for providing a leading edge implementation, especially when compared with the complementary FET (CFET) architectures being proposed for process nodes below 1nm.
“Computing power is moving much faster than memory, there is a memory wall and we cannot take advantage of the scaling of transistors,” said Lequepeys. “Without having faster memory it is difficult to take advantage of leading processes and CFET transistors. We have no idea how to build memories to take advantage of CFET technology today.”
This is driving a move away from large datacentres and new approaches to AI, he says, and the chips will follow.
“For AI we need two types of memory, with non-volatile memory to store the weights and a working memory. We need denser memories and my feel is that we will move from large language models (LLMs) to small language models (SLMs) to limit the requirements, for selective applications, so there will be several kinds of AI. ChatGPT consumes too much power to be able to scale.
“If we manage data at the edge rather than in the cloud, there is 1m difference, that’s why we need to process data as soon as possible and send data to the cloud only when necessary. Today only 10% of the data is processed at the edge. By 2030 that could be as much as 80% for the low latency as well as for the lower power consumption and it protects our data as well.”
CEA-Leti has used the two years since the announcement of the setting up of the line to develop the underlying design infrastructure and a pipeline of projects. An open call this time last year aimed to stimulate projects from a range of developers outside of the stakeholders.
“Within the framework of the FAMES pilot line, we have a €333 million investment for CEA-Leti, enabling the acquisition of approximately 80 pieces of equipment, including metrology and characterization tools. For lithography, we have acquired a TWINSCAN NXT-2050i, a deep UV (DUV) lithography system.”
“We decided to go with this tool to have lower cost in the end as we can go down to 7nm, after that to go to 5nm we have to go to EUV which is much more expensive. So we use the right lithography for the right chips.”
“FAMES will create new market opportunities for low-power microcontrollers (MCU), multi-processor units (MPU), cutting-edge AI and Machine Learning devices, smart data-fusion processors, RF devices, chips for 5G/6G, chips for automotive markets, smart sensors and imagers, trusted chips and new space components,” he said.
He points to 44 industry stakeholders that have already supported the FAMES initiative, including: telecoms developers Nokia and Ericsson, industrial giant Siemens and automotive suppliers Stellantis, Forvia, Valeo and Bosch. But Intel, Meta and IBM are also involved, giving the potential for leading edge AI chip designs, while industrial chip maker STMicroelectronics, foundry GlobalFoundries and French wafer supplier Soitec are also partners.
The FD SOI technology also benefits the billions of devices rolling out for the Internet of Things (IoT). The most advanced FD SOI technology is current a 22nm process at GlobalFoundries, 22FDX. It is spending €1.1 billion to expand its manufacturing capabilities at its Dresden, Germany site. The investment will enable a production capacity increase to more than one million wafers per year by the end of 2028, making it the largest site of its kind in Europe.
“It’s very nice for IoT devices where you can cut the power supply and save parameters and start again very rapidly. If we look at 22FDX at GlobalFoundries after transferring the technology we have to wait 3 years and now they are in full business and the market is still progressing. That’s why they need to announce the next node to open up the market,” said Lequepeys.
As a part of the project, called SPRINT, the Dresden facility will be upgraded to offer end-to-end European processes and data flows for critical semiconductor security requirements.
“The SPRINT project is a commitment to Germany as an industrial and innovation location – and above all to the sovereignty of our country and Europe,” said German Chancellor Friedrich Merz. “The investment in chip manufacturing in Dresden sends a signal that Germany wants to play an active role in shaping the development of the global semiconductor market. Germany already plays a leading role in microelectronics in Europe.”
“Recent disruptions in the automotive sector underscore just how vulnerable global chip supply chains truly are. Our planned expansion in Dresden is yet another step in GF’s strategy to address these challenges head-on and deliver on our commitment to support Europe’s need for secure supply chains and differentiated technologies,” said Tim Breen, CEO of GlobalFoundries. “By scaling our manufacturing footprint in Europe, in the U.S. and around the world, GF is reinforcing its role as a resilient and trusted partner to customers in critical industries and building a foundation for the next wave of innovation as physical AI becomes reality.”
EDA tools
EDA tools however are a key issue. The design tools for planar are simpler than for FinFET, Intel’s RibbonFET or Samsung’s and TSMC’s Gate All Around (GAA) transistors used at 2nm, and both Synopsys and Cadence Design Systems have tool flows for the 22nm FDX process at Global Foundries. However modelling and design tools for 7nm FD SOI will be required with multiple layers of logic, memory and RF.
There is also a technique for FD-SOI called active body bias where the voltage of the transistors can be adjusted to trade-off power consumption and performance. This needs to be included in the design tools.
“We have some EDA vendors such as Dolphin Integration for body bias EDA tools to help designers and this add on is provided in GlobalFoundries,” said Lequepeys. “We stimulate the demand – if there is a big demand we need the tools.”
Part of the problem is the demand is much greater for FinFET tools, but that can be used as an advantage, he says.
“FD-SOI is 4% [of designs] vs 96% for FinFET so the EDA vendors focus on that,” he said. “I would take in a different way. With 3D designs we could have FinFET with the digital elements and then an FD-SOI layer for analog and RF, three or four layers of interconnect and then build on top so we get the advantage of FinFET and FD-SOI. My feeling is to get the 3nm or 4nm FinFet wafers and develop the FD-SOI chip on top.
“In the front end of line we stack several layers of transistors, then put a thin layer of SOI to develop the second stage. This sequential integration is a nice way to go to increase performance and decrease the performance and the size of the chip,” he said.
A process development kit for 10nm FD-SOI designs has already been developed and is with early adopters as the pilot line opens.
“For IC designers, FD-SOI offers unique opportunity to use the back gate of the transistors to modulate the Voltage Threshold of the transistors. A pathfinding PDK for the 10FD-SOI node was designed and is being distributed to early users. This PDK will help gain feedback from external IC designers,” he said.
Sub-2nm process technology
That isn’t to downplay the role that Europe has in developing leading edge digital process technology. The NanoIC pilot line, which will be fully up and running next month, will provide chip-making technology for leading edge fabs in Taiwan and Korea, and later in the US. Just not in Europe.
“Since announcing in May 2024 that imec would host the NanoIC pilot line, we’ve moved at full speed – accelerating tool acquisition and launching a comprehensive recruitment program. That effort culminates in the inauguration of a 2000m² cleanroom extension at the imec premises. It will house a best-in-class toolset, including ASML’s next-generation High NA EUV scanner that is scheduled to arrive mid-March,” said Luc Van den hove, CEO of imec in Belgium.
“We have embarked on an ambitious journey to push semiconductor technologies beyond the 2nm node. By providing access to cutting-edge semiconductor technologies, the NanoIC pilot line will play a crucial role in strengthening Europe’s industrial fabric in the AI era, and ensuring a climate of economic growth, security, and prosperity for decades to come,” he added.
While there will be a leading edge fab in Europe, with a new 4000 m² cleanroom to house the pilot line, it is not a commercial fab. Over the next five years, the NanoIC pilot line will integrate more than a hundred new tools, distributed across imec and partner sites at CEA-Leti, Fraunhofer in Germany, VTT in Finland, CSSNT-UPB in Romania and Tyndall National Institute in Ireland.
As geopolitical and trade issues challenge the global semiconductor supply chain, the need for leading edge process technology that can be produced in Europe becomes more apparent. The FAMES pilot line for FD SOI marks a key opportunity for Europe to produce leading edge chips over the next five years, just not in the way one might expect.
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